In the name of GOD

Home Page of

Ehsan Kh. Ardestani Zadeh

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Experiences

 

My current work in VoIP processor group :

See VoIP Processor   

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Developing an Embedded processor, called TMIPS, for packet processing and overall control of others modules.

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Porting TCP/IP and RTP/UDP/IP Protocol stacks on TMIPS.

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Developing PCI bridge for TMIPS.

 

Past projects:

  Design and Implementation of
  Line Follower Robot (2001)
        - Include Infrared sensor, Stepper motor driver and Logic circuits.
  Labyrinths Robot ( 2002)
        - Include Ultrasonic, Microcontroller, PC interfacing and Motor Driver circuits.
  Mine Detector Robot  (2003)
        - Include Metal detector, Control Motor (PWM), Microcontroller, PC Interfacing circuits and etc.
        - BS Final project (20/20).
  PCI Host bridge IP core (2004)
        - 32 bit, 33 MHz, Master, Slave and Host interfaces
        - On Xilnx (Spartan II) and Altera (Excalibur) FPGAs
        - AMBA AHB interface in back-end.
        - Attached to Global processor in VoIP processor to enable its communication with outside world.
  UTOPIA Controller level 2 IP core  (2006)
  WISHBONE Interconnection IP core (2006)
        -  On Spartan 3
  Programmable HDLC Controller IP core (2006)
        - on ACEX
        - Intel bus interface in its back-end side
        - Clock recovery enabled.
        - Collision detection/resolution
        - Bit stuffing (both Zero and One)
        - Dual Channel
        - Employed in ICII OAX system.
  PCI Linux Device driver
        - on Redhat Kernel version 2.4
 
  A System-level Architecture for Video Coding (2005-2006)
        - My MSc Thesis. Concluded with excellent grade (20/20).
        - In this project, I have designed a pipelined coprocessor beside a RISC core (MIPS) to
          accelerate the common computation intensive operation in video codecs such as MPEG-2
          and H.264/AVC.A bus functional, clock accurate simulator in systemC is developed for
          evaluation.
 
 Development of a General Purpose Embedded Processor (2006)
        - MIPS ISA
        - 2 separate caches for both Data and Program
        - Vector Interrupt Controller
        - AMBA AHB Bus Interface
        - ...
My current occupation:
  Chief Designer in VoIP Processor Group (2004-present)
        - Design a VoIP processor and its verification on FPGA
        - Comprising
            - a boosted MIPS RISC core for signal processing
            - a Leon processor for packet processing (will be replaced by TMIPS)
            - AMBA AHB interconnection
            - Ethernet MAC
            - PCI bus interface (Host, Master, Slave)
            - ...
  Chief Designer at Ava semiconductor (present)
         - Design and ASIC implementation of a VoIP processor.
 Chief Designer in NGN developer group at ICII.(present)
        - IPDSLAM
            - PCI Host/Bridge
            - ATM Core
            - Network Processor
        - EFM
 

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Last updated: 15/Dec/2006.