Naser Mohammadzadeh

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Mobirise

Associate Professor of Computer Engineering
Shahed University
Email: Mohammadzadeh [at] shahed.ac.ir
Phone: (+98) 21-51212098
Fax: (+98) 21-51212021
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1999- 2003

B.Sc. in Computer Engineering,

Computer Engineering Department, Sharif University of Technology, Tehran, Iran.

Advisor:
Prof. Mohammad Taghi Manzuri

2003- 2005

M.Sc. in Computer Engineering 

Computer Engineering Department, Sharif University of Technology, Tehran, Iran.

Advisor:
Prof. Shahin Hesabi

2007 - 2010

Ph.D. in Computer Engineering 

Computer Engineering Department, Amirkabir University of Technology, Tehran, Iran.

Advisor:
Prof. Morteza SahebZamani &
Prof. Mehdi Sedighi

RESEARCH INTERESTS

- Quantum Design Automation
         o Optimization
         o Logic Synthesis
         o Physical Design
- Electronic Design Automation
        o Floorplanning
        o Placement and Routing
        o Logic and Physical Synthesis
- Hardware/Software Co-design
- Algorithms for search and optimization
- Electronic System-Level Design (Odyssey Project)                

AREA of SPECIALTY                                                                               

- Quantum Design Automation
           o Physical Design
           o Logic Synthesis
- Classical Design Automation
- Design Verification and Validation
- Embedded System Design
- Reconfigurable Systems 

AWARDS and HONORS

- Distinguished researcher, Department of Computer Engineering, Shahed University, in 2016.

Second position in FPGA Design Contest (FDC) [Path Follower Robot], Sharif University of Technology, 2001 

PUBLICATIONS

1. Maziar Goudarzi, Naser Mohammadzadeh, and Shaahin Hessabi, "Using On-Chip Networks to Implement Polymorphism in the Co-design of Object-Oriented Embedded Systems," Elsevier Journal of Computer and System Sciences (JCSS), Vol. 73, No. 8, 2007.

2. Maziar Goudarzi, Shaahin Hessabi, Naser Mohammadzadeh, and Nasim Zainolabedini, "The ODYSSEY Approach to Early Simulation-based Equivalence-Checking at ESL Level using Automatically-Generated Executable Transaction-Level Model," Elsevier Journal of Microprocessors and Microsystems (MICPRO), Vol. 32, No. 7, 2008.

3. Naser Mohammadzadeh, Maziar Goudarzi, Shaahin Hessabi,and Mahdi Maleki, "A Framework for Object-Oriented Embedded System Development Based on OO-ASIPs," World Scientific Journal of Circuits, Systems, and Computers (JCSC), Vol. 17, No. 6, 2008.

4. Mehdi Saeedi, Naser Mohammadzadeh, Mehdi Sedighi, and Morteza Saheb Zamani, "Towards a Thorough Set of Metrics for Quantum Circuit Synthesis," International Journal of Physics, 2008.

5. Naser Mohammadzadeh, Mehdi Sedighi, and Morteza Saheb Zamani, "Quantum Physical Synthesis: Improving Physical Design by Netlist Modifications," Elsevier Microelectronics Journal, Vol. 41, 2010.

6. Naser Mohammadzadeh, Morteza Saheb Zamani, and Mehdi Sedighi, "Auxiliary Qubit Selection: A Physical Synthesis Technique for Quantum Circuits," Springer Quantum Information Processing Journal (QINP), Vol. 10, No. 2, 2011.

7. Naser Mohammadzadeh, Mehdi Sedighi, and Morteza Saheb Zamani, "Gate Location changing: An Optimization Technique for Quantum Circuits,” World Scientific International Journal of Quantum Information (IJQI), Vol. 10, No, 3, 2012.

8. Naser Mohammadzadeh, Morteza Saheb Zamani, and Mehdi Sedighi,"Quantum Circuit Physical Design Methodology with Emphasis on Physical Synthesis," Quantum Information Processing Journal (QINP), Vol.13, No. 2, 2014.

9. Mahbubeh Raeisi and Naser Mohammadzadeh, "Scheduling Physical Operations in Quantum Circuits using a Greedy Algorithm," International Journal of Electrical Energy, Vol. 2, No. 3, September 2014.

10. Naser Mohammadzadeh, Tayebeh Bahreini, and Hosein Badri, "Optimal ILP-Based Approach for Gate Location Assignment and Scheduling in Quantum Circuits," Modelling and Simulation in Engineering, Vol. 2014, 2014.

11. Tayebeh Bahreini and Naser Mohammadzadeh, "An MINLP Model for Scheduling and Placement of Quantum Circuits with a Heuristic Solution Approach," ACM Journal of Emerging Technologies, Vol. 12, No. 3, 2015.

12. Naser Mohammadzadeh and Elaheh Taqavi, "Quantum Circuit Physical Design Flow for the Multiplexed Ion Trap Architecture," Microprocessors and Microsystems Journal, VOl. 45, Part A, 2016.

13. Yaser Taheri, Hossein Gharaee Garakani, and Naser Mohammadzadeh, “A Game Theory Approach for Malicious Node Detection in MANETs,” Journal of Information Science and Engineering, Vol. 32, No. 2, 2016.

14. Zahra Mirkhani and Naser Mohammadzadeh, “Physical Synthesis of Quantum Circuits using Templates,” Quantum Information Processing, Vol. 15, No. 10, 2016.

15. Naser Mohammadzadeh, "Physical Design of Quantum Circuits in Ion Trap Technology - A Survey," Vol. 55, Microelectronics Journal, 2016.

16. Mahdie Kiaee, Hossein Gharaee, and Naser Mohammadzadeh, "A High-Throughput FPGA Implementation of Quasi-Cyclic LDPC Decoder," International Journal of Computer Science and Network Security (IJCSNS), Vol. 17, No. 3, 2017.

17. Azim Farghadan and Naser Mohammadzadeh, "Quantum Circuit Physical Design Flow for 2D nearest neighbor architectures," International Journal of Circuit Theory and Applications, Vol. 45, No. 7, 2017.

18. Hanieh Ghaffarishad, Naser Mohammadzadeh, and Mohammad-Bagher Ghaznavi-Ghoushchi,"A Power-Performance Tunable Logic with Adjustable Threshold Pseudo-Dynamic Building Blocks and CMOS Compatibility," International Journal of Circuit Theory and Applications, Vol. 46, No. 4, 2018.

19. Sahar Sargaran and Naser Mohammadzadeh, “SAQIP A Scalable Architecture for Quantum Information Processors,” ACM Transactions on Architecture and Code Optimization, under review, 2018. 

20. Elham Serkani, Hossein Gharaee Garakani, Naser Mohammadzadeh, Elaheh Vaezpour, "Hybrid Anomaly Detection Using Decision Tree and Support Vector Machine," International Journal of Electrical and Computer Engineering
Vol:12, No:6, 2018 

1. Mina Moghaddam, Naser Mohammadzadeh, Mehdi Sedighi, and Morteza Sahebzamani, "A Hierarchical Layout Generation Method for Quantum Circuits," CADS, Tehran, Iran, 2013.

2. Naser Mohammadzadeh, Morteza Saheb Zamani, and Mehdi Sedighi, "Improving Latency of Quantum Circuits by Gate Exchanging," DSD, Patras, Greece, 2009.

3. Naser mohammadzadeh, Minoo Mirsaeedi, Ali Jahanian, and Morteza Saheb Zamani, “Multi-Domain Clock Skew Scheduling-Aware Register Placement to Optimize Clock Distribution Network,” DATE, Nice, France, 2009.

4. Mehdi Saeedi, Naser Mohammadzadeh, Mehdi Sedighi, and Morteza Saheb Zamani, "Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics, DSD, Parma, Italy, 2008.

5. Naser Mohammadzadeh, Morteza Najafvand, Shaahin Hesabi, and Maziar Goudarzi, "Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology," GLSVLSI, Stresa-Lago Maggiore, Italy, 2007.

6. Naser Mohammadzadeh, Shaahin Hessabi, and Maziar Goudarzi, "Evolving an MPEG2 Processor from a JPEG Object-Oriented ASIP: A Case Study on a System-Level Design methodology," CSICC, Tehran, Iran, 2006.

7. Mehdi Modarresi, Hani Javanhemmat, Seyyed Ghasem Miremadi, Shaahin Hessabi, Morteza Najafvand, Maziar Goudarzi, and Naser Mohamadzadeh, "A Fault-Tolerant Approach to Embedded-System Design Using Software Standby Sparing,"CSICC, Tehran, Iran, 2006.

8. Naser Mohammadzdeh, Shaahin Hessabi, and Maziar Goudarzi, "Software Implementation of MPEG2 Decoder on an ASIP JPEG Processor," ICM, Islamabad, Pakistan, 2005.

9. Mahdie Kiaee, Hossein Gharaee, and Naser Mohammadzadeh, "LDPC Decoder Implementation using FPGA," 8th International Symposium on Telecommunications (IST), 2016.

10. Shadi Janbabaei, Hossein Gharaee, and Naser Mohammadzadeh, "Lightweight, Anonymous, and Mutual Authentication in IoT Infrastructure," 8th International Symposium on Telecommunications (IST), 2016.

11. Shadi Janbabaei, Hossein Gharaee, and Naser Mohammadzadeh, "Mutual Authentication for Sensor-To-Sensor Communications in IoT Infrastructure," 19th International Conference on Computer Systems Engineering and Technology, Paris, 2017. 

Mobirise

Teaching

Postgraduate

o Quantum Computation and Quantum Information (QCQI)
o Electronic Design Automation (EDA)
o Hardware Systems Modeling and Design Methodologies 

Undergraduate 

o VLSI Design 
o Digital System Design (DSD)
o Computer Architecture 

Address

Faculty of Engineering,
Shahed University, Persian-Gulf Freeway, Tehran, Iran 


Contacts

Email: mohammadzadeh@shahed.ac.ir
          
Phone: +98 (21) 5121 2098 
Fax:      +98 (21) 5121 2021