VLSI Slides


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EDA\01_intro_CAD-.ppt

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EDA\02_designstyles-.ppt

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EDA\04_fab-.ppt

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EDA\05_fab1-.ppt

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EDA\06_fab_designrules-.ppt

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EDA\07_graph-.ppt

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EDA\08_algorithms-.ppt

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EDA\09_algorithms-.ppt

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EDA\10_datastructures-.ppt

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EDA\11_cstitch-GDSII-.ppt

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EDA\13_partition-.pptx

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EDA\14_1partition-FM-.ppt

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EDA\14_3partition-ML and FPGA-.ppt

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EDA\15-0-Chip Planning-FP1-.pptx

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EDA\15-1_floorplanning_SA-sequence_pair-.ppt

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EDA\15-2- floor sizing-FP2-.pptx

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EDA\16_floorplanning_SA-reverse polish--.ppt

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EDA\17-pin assignment-.pptx

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EDA\17-Power routing-p-.pptx

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EDA\18-placement-.pptx

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EDA\19-placement-mincut-.pptx

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EDA\20-placement-Analytic-FD-BB-.pptx

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EDA\21-placement-SA-congestion-.pptx

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EDA\22-placement genetic-.ppt

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EDA\23-placement-modern-legalization-detailed-.pptx

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EDA\24-global routing-.pptx

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EDA\25-global routing-single net-.pptx

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EDA\26-global routing-full net-.pptx

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EDA\27_maze_routing-.ppt

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EDA\28_maze_routing-.ppt

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EDA\29-global routing-ILP-RRR-NCR-.pptx

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EDA\31_detailed_routing-.ppt

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EDA\33_detailed_routing-LEA-.ppt

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EDA\34_detailed_routing-sb-x-.ppt

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EDA\35-detailed_routing-new-chlgs-.pptx

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EDA\36_DFM_OPC-.ppt

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EDA\40_2_STA.ppt

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EDA\40_physical synthesis.ppt

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EDA\41_1_variation-.ppt

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EDA\41_2_SSTA-.ppt

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EDA\41_3_SSTA Approaches-.ppt

 

 


 

 

 

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